/*
 * Copyright (C) 2016 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See http://www.gnu.org/licenses/gpl-2.0.html for more details.
 */

#ifndef __MT_IOMMU_PORT_H__
#define __MT_IOMMU_PORT_H__
/*
 * this header file is only used for mtk_iomm module
 * the definition of header file is platform dependency.
 */
//enable this option if M4U new design of multiple bank
//#define IOMMU_DESIGN_OF_BANK

struct mtk_iommu_port {
	char *name;
	unsigned m4u_id: 2;
	unsigned m4u_slave: 2;
	unsigned larb_id: 4;
	unsigned larb_port: 8;
	unsigned tf_id: 12;     /* 12 bits */
	bool enable_tf;
	mtk_iommu_fault_callback_t fault_fn;
	void *fault_data;
};

#define MTK_IOMMU_PORT_INIT(name, slave, larb, port)  {\
	name, 0, slave, larb, port, (((larb)<<7)|((port)<<2)), 1\
}

#define M4U_SLAVE0 (0)
#define M4U_SLAVE1 (0)
#define M4U_SLAVE2 (0)
#define M4U_SLAVE3 (0)
#define M4U_SLAVE4 (0)

#define M4U_LARB0 (0)
#define M4U_LARB1 (1)
#define M4U_LARB2 (2)
#define M4U_LARB3 (3)
#define M4U_LARB4 (4)
#define MTK_IOMMU_LARB_NR (5)

struct mtk_iommu_port iommu_port[] = {
	/*Larb0 */
	MTK_IOMMU_PORT_INIT("DISP_OVL0", M4U_SLAVE0, M4U_LARB0, 0),
	MTK_IOMMU_PORT_INIT("DISP_2L_OVL0_LARB0", M4U_SLAVE0, M4U_LARB0, 1),
	MTK_IOMMU_PORT_INIT("DISP_RDMA0", M4U_SLAVE0, M4U_LARB0, 2),
	MTK_IOMMU_PORT_INIT("DISP_WDMA0", M4U_SLAVE0, M4U_LARB0, 3),
	MTK_IOMMU_PORT_INIT("MDP_RDMA0", M4U_SLAVE0, M4U_LARB0, 4),
	MTK_IOMMU_PORT_INIT("MDP_WDMA0", M4U_SLAVE0, M4U_LARB0, 5),
	MTK_IOMMU_PORT_INIT("MDP_WROT0", M4U_SLAVE0, M4U_LARB0, 6),
	MTK_IOMMU_PORT_INIT("DISP_FAKE0", M4U_SLAVE0, M4U_LARB0, 7),
	/*Larb1 */
	MTK_IOMMU_PORT_INIT("VDEC_MC", M4U_SLAVE1, M4U_LARB1, 0),
	MTK_IOMMU_PORT_INIT("VDEC_PP", M4U_SLAVE1, M4U_LARB1, 1),
	MTK_IOMMU_PORT_INIT("VDEC_VLD", M4U_SLAVE1, M4U_LARB1, 2),
	MTK_IOMMU_PORT_INIT("VDEC_VLD2", M4U_SLAVE1, M4U_LARB1, 3),
	MTK_IOMMU_PORT_INIT("VDEC_AVC_MV", M4U_SLAVE1, M4U_LARB1, 4),
	MTK_IOMMU_PORT_INIT("VDEC_PRED_RD", M4U_SLAVE1, M4U_LARB1, 5),
	MTK_IOMMU_PORT_INIT("VDEC_PRED_WR", M4U_SLAVE1, M4U_LARB1, 6),
	MTK_IOMMU_PORT_INIT("VDEC_PPWRAP", M4U_SLAVE1, M4U_LARB1, 7),
	MTK_IOMMU_PORT_INIT("VDEC_TILE", M4U_SLAVE1, M4U_LARB1, 8),
	/*Larb2 */
	MTK_IOMMU_PORT_INIT("CAM_IMGI", M4U_SLAVE2, M4U_LARB2, 0),
	MTK_IOMMU_PORT_INIT("CAM_IMG2O", M4U_SLAVE2, M4U_LARB2, 1),
	MTK_IOMMU_PORT_INIT("CAM_IMG3O", M4U_SLAVE2, M4U_LARB2, 2),
	MTK_IOMMU_PORT_INIT("CAM_VIPI", M4U_SLAVE2, M4U_LARB2, 3),
	MTK_IOMMU_PORT_INIT("CAM_LCEI", M4U_SLAVE2, M4U_LARB2, 4),
	MTK_IOMMU_PORT_INIT("CAM_FD_RP", M4U_SLAVE2, M4U_LARB2, 5),
	MTK_IOMMU_PORT_INIT("CAM_FD_WR", M4U_SLAVE2, M4U_LARB2, 6),
	MTK_IOMMU_PORT_INIT("CAM_FD_RB", M4U_SLAVE2, M4U_LARB2, 7),
	MTK_IOMMU_PORT_INIT("CAM_DPE_RDMA", M4U_SLAVE2, M4U_LARB2, 8),
	MTK_IOMMU_PORT_INIT("CAM_DPE_WDMA", M4U_SLAVE2, M4U_LARB2, 9),
	MTK_IOMMU_PORT_INIT("CAM_RSC_RDMA", M4U_SLAVE2, M4U_LARB2, 10),
	MTK_IOMMU_PORT_INIT("CAM_RSC_WDMA", M4U_SLAVE2, M4U_LARB2, 11),
	/*Larb3 */
	MTK_IOMMU_PORT_INIT("CAM_IMGO", M4U_SLAVE3, M4U_LARB3, 0),
	MTK_IOMMU_PORT_INIT("CAM_RRZO", M4U_SLAVE3, M4U_LARB3, 1),
	MTK_IOMMU_PORT_INIT("CAM_AAO", M4U_SLAVE3, M4U_LARB3, 2),
	MTK_IOMMU_PORT_INIT("CAM_AFO", M4U_SLAVE3, M4U_LARB3, 3),
	MTK_IOMMU_PORT_INIT("CAM_LSCI0", M4U_SLAVE3, M4U_LARB3, 4),
	MTK_IOMMU_PORT_INIT("CAM_LSCI1", M4U_SLAVE3, M4U_LARB3, 5),
	MTK_IOMMU_PORT_INIT("CAM_PDO", M4U_SLAVE3, M4U_LARB3, 6),
	MTK_IOMMU_PORT_INIT("CAM_BPCI", M4U_SLAVE3, M4U_LARB3, 7),
	MTK_IOMMU_PORT_INIT("CAM_LCSO", M4U_SLAVE3, M4U_LARB3, 8),
	MTK_IOMMU_PORT_INIT("CAM_RSSO_A", M4U_SLAVE3, M4U_LARB3, 9),
	MTK_IOMMU_PORT_INIT("CAM_RSSO_B", M4U_SLAVE3, M4U_LARB3, 10),
	MTK_IOMMU_PORT_INIT("CAM_UFEO", M4U_SLAVE3, M4U_LARB3, 11),
	MTK_IOMMU_PORT_INIT("CAM_SOCO", M4U_SLAVE3, M4U_LARB3, 12),
	MTK_IOMMU_PORT_INIT("CAM_SOC1", M4U_SLAVE3, M4U_LARB3, 13),
	MTK_IOMMU_PORT_INIT("CAM_SOC2", M4U_SLAVE3, M4U_LARB3, 14),
	MTK_IOMMU_PORT_INIT("CAM_CCUI", M4U_SLAVE3, M4U_LARB3, 15),
	MTK_IOMMU_PORT_INIT("CAM_CCUO", M4U_SLAVE3, M4U_LARB3, 16),
	MTK_IOMMU_PORT_INIT("CAM_CACI", M4U_SLAVE3, M4U_LARB3, 17),
	MTK_IOMMU_PORT_INIT("CAM_RAWI_A", M4U_SLAVE3, M4U_LARB3, 18),
	MTK_IOMMU_PORT_INIT("CAM_RAWI_B", M4U_SLAVE3, M4U_LARB3, 19),
	MTK_IOMMU_PORT_INIT("CAM_CCUG", M4U_SLAVE3, M4U_LARB3, 20),
	/*Larb4 */
	MTK_IOMMU_PORT_INIT("VENC_RCPU", M4U_SLAVE4, M4U_LARB4, 0),
	MTK_IOMMU_PORT_INIT("VENC_REC", M4U_SLAVE4, M4U_LARB4, 1),
	MTK_IOMMU_PORT_INIT("VENC_BSDMA", M4U_SLAVE4, M4U_LARB4, 2),
	MTK_IOMMU_PORT_INIT("VENC_SV_COMV", M4U_SLAVE4, M4U_LARB4, 3),
	MTK_IOMMU_PORT_INIT("VENC_RD_COMV", M4U_SLAVE4, M4U_LARB4, 4),
	MTK_IOMMU_PORT_INIT("JPGENC_RDMA", M4U_SLAVE4, M4U_LARB4, 5),
	MTK_IOMMU_PORT_INIT("JPGENC_BSDMA", M4U_SLAVE4, M4U_LARB4, 6),
	MTK_IOMMU_PORT_INIT("VENC_CUR_LUMA", M4U_SLAVE4, M4U_LARB4, 7),
	MTK_IOMMU_PORT_INIT("VENC_CUR_CHROMA", M4U_SLAVE4, M4U_LARB4, 8),
	MTK_IOMMU_PORT_INIT("VENC_REF_LUMA", M4U_SLAVE4, M4U_LARB4, 9),
	MTK_IOMMU_PORT_INIT("VENC_REF_CHROMA", M4U_SLAVE4, M4U_LARB4, 10),

	MTK_IOMMU_PORT_INIT("UNKNOWN", 0, 0, 0)
};

#ifndef M4U_PORT_NR
#define M4U_PORT_NR (61)
#endif

#endif
